The present invention relates to distributing reference clock signals to individual system modules and more particularly to distributing clock signals to support synchronous system operations.
Advances in microprocessor development have resulted in ever-faster processing speeds, now measured in frequencies of hundreds of megacycles-per-second. In systems such as Fault-Tolerant Computers (FTC) operating in a synchronous, lock-step manner, inter-module clock phase alignment is critical. Each of the individual system modules operating at their respective high frequency require a suitable reference clock to allow system synchronization. In addition to phase alignment within lock-step FTC systems, it is also critical that processors maintain their lock step relationship (performing the same instructions on the same clock cycle) through reset events.
One method for ensuring that processors maintain lock-step relationship is to distribute the high-frequency clock directly. Distributing clock signals at high frequencies, however, exposes them to adverse effects of transmission line distortion, system noise and radio-frequency interference. As a result, these high-frequency system clocks can become corrupted to the point that clock phase detection becomes difficult. Further, as clock cycle time shrinks, clock distribution circuitry becomes less tolerant of clock skew and jitter introduced by the distribution circuit. Mitigating these adverse high-frequency effects complicates system design.
A further problem with distributing the high-frequency clock signal directly is that the lower-frequency clock signals that are commonly used by components on a module must be generated. Generating these local timing signals requires dividing the incoming system clock into the one or more lower-frequency clock signals. A common method in systems that distribute lower frequency reference clocks uses a 14.38% MHz reference clock. Intel Pentium-based systems operate at system clock rates that are multiples of 33 MHz (i.e., 33 MHz, 100 MHz, and 133 MHz). Use of the 14.38 MHz reference within the Pentium-based systems unavoidably requires an initial division of the reference clock, because 14.38 MHz is not a common divisor of the Pentium-based system clock rates. The division step adds a differential phase delay between system components. This added delay further complicates system design, because the resulting differential phase delay must be normalized across the components on a module to maintain necessary synchronized, lock-step operation. The present invention avoids these problems.
The present invention relates to methods and apparatus for distributing clock signals in a multi-module system. One object of this invention is to maintain synchronization of all system modules. In one embodiment of the invention, a single reference clock signal is distributed to each system module, arriving there within a prescribed window of time. Local clock signals are generated at each system module from the reference clock. In one embodiment, a phase locked loop (PLL) is used to generate the local clock signals. One aspect is that the operating frequency of the reference clock signal is a common divisor to all local clock signals. Another aspect is that the rising edge of the local clock signal is coincident with the rising edge of the reference clock signal. Yet another aspect is that signal distribution of the lower frequency reference clock avoids complications associated with distributing a high-frequency reference clock operating at the local clock rates.
In one embodiment of the invention, a master timing signal is provided as a reference. This timing signal is identified as the first rising edge of the system reference clock occurring after a some system event, such as a reset.